(1) Field of the Invention
This invention relates to a flash memory cell and more particularly to a P-channel flash memory cell using source side injection hot electron tunneling for programming the cell, and a sharp edge on the control gate and Fowler-Nordheim tunneling for erasing the cell.
(2) Description of the Related Art
U.S. Pat. No. 5,706,227 to Chang et al. describes a split gate P-channel flash memory cell which uses electron tunneling from the floating gate into the N-well for erasing the cell.
U.S. Pat. No. 5,480,821 to Chang describes source coupled N-channel split gate flash memory cells.
U.S. Pat. No. 5,067,108 to Jenq describes a flash memory cell using hot electron injection into the floating gate to program the cell and Fowler-Nordheim tunneling of electrons from the floating gate to the control gate to erase the cell.
U.S. Pat. No. 5,652,161 to Ahn describes a method of forming a split gate flash EEPROM cell.
Flash memory cells are find frequent use in electrically programmable read only memory cells. N-channel flash memory cells however have a problem of reverse tunneling affecting unselected cells due to the bias voltages applied during programming of selected cells. Nitride spacers are frequently required to avoid this problem of reverse tunneling. P-channel flash memory cells using a double polysilicon split gate have a disadvantage of requiring a high erasing voltage and thin tunnel oxide. P-channel stacked gate flash memory cells suffer from drain disturb problems and over-erase problems. The ability to shrink N-channel flash memory cells is limited by the distance required between the source and drain junctions and the required length of the floating gate in order to create sufficient hot electrons to program the cell.
It is a principle objective of this invention to provide a method of forming a split gate P-channel flash memory cell which avoids these problems of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions.
It is another principle objective of this invention to provide a split gate P-channel flash memory cell which avoids these problems of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions.
These objectives are achieved by using a P-channel polysilicon split gate flash memory cell. The P-channel split gate flash memory cell has a floating gate and a control gate and a sharp edge on the floating gate. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The floating gate is fabricated with a concave top surface so that a sharp edge is formed at the intersection of the concave top surface and the sidewalls of the floating gate. The sharp edge produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate.
The length of the floating gate can be kept small so that the flash memory cell can be shrunk to small dimensions.